DK-DEV-5SGXEA7N【PDF 79/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51005

2014.01.10

Clock Network Sources

4-9

Figure 4-10: Dual-Regional Clock Region for Stratix V Devices

This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.

Clock pins or PLL outputs can

drive half of the device to create

dual-regional clocking regions

for improved interface timing.

Clock Network Sources

In Stratix V devices, clock input pins, PLL outputs, high-speed serial interface (HSSI) outputs, DPA outputs,

and internal logic can drive the GCLK, RCLK, and PCLK networks.

Dedicated Clock Input Pins

You can use the dedicated clock input pins (CLK[0..23][p,n]) for high fan-out control signals, such as

asynchronous clears, presets, and clock enables, for protocol signals through the GCLK or RCLK networks.

CLK pins can be either differential clocks or single-ended clocks. When you use the CLK pins as single-ended

clock inputs, only the CLK<#>p pins have dedicated connections to the PLL. The CLK<#>n pins drive the PLLs

over global or regional clock networks and do not have dedicated routing paths to the PLLs.

Driving a PLL over a global or regional clock can lead to higher jitter at the PLL input, and the PLL will not

be able to fully compensate for the global or regional clock. Altera recommends using the CLK<#>p pins for

optimal performance when you use single-ended clock inputs to drive the PLLs.

Internal Logic

You can drive each GCLK, RCLK, and horizontal PCLK network using LAB-routing and row clock to enable

internal logic to drive a high fan-out, low-skew signal.

Note: Internally-generated GCLKs, RCLKs, or PCLKs cannot drive the Stratix V PLLs. The input clock to

the PLL has to come from dedicated clock input pins, PLL-fed GCLKs, or PLL-fed RCLKs.

DPA Outputs

Every DPA generates one PCLK to the core.

Related Information

High-Speed I/O Design Guidelines for Stratix V Devices on page 6-8

Provides more information about DPA and HSSI outputs.

Clock Networks and PLLs in Stratix V Devices

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